`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/18 12:10:16
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
input logic clk,
input logic rst_n,
input logic start
    );
//sel和start信号
assign m0_sel_w=0;                    //主机0写从机0
assign m1_sel_w=0;                    //主机1写从机0
assign m2_sel_w=1;                    //主机2写从机1
assign m3_sel_w=1;                    //主机3写从机1
assign m0_sel_r=0;
assign m1_sel_r=0;
assign m2_sel_r=1;
assign m3_sel_r=1;
//
//
initial
begin
   start0_r=0;
   #(10000+2+($urandom%100)*10)
   start0_r=1;
   #10
   start0_r=0;
end
initial
begin
   start1_r=0;
   #(10000+2+($urandom%100)*10)
   start1_r=1;
   #10
   start1_r=0;
end
initial
begin
   start2_r=0;
   #(10000+2+($urandom%100)*10)
   start2_r=1;
   #10
   start2_r=0;
end
initial
begin
   start3_r=0;
   #(10000+2+($urandom%100)*10)
   start3_r=1;
   #10
   start3_r=0;
end
//
initial
begin
    start0_w=0;
	#(102+($urandom%100)*10)
	start0_w=1;
	#10
	start0_w=0;
end
initial
begin
    start1_w=0;
	#(102+($urandom%100)*10)
	start1_w=1;
	#10
	start1_w=0;
end
initial
begin
    start2_w=0;
	#(102+($urandom%100)*10)
	start2_w=1;
	#10
	start2_w=0;
end
initial
begin
    start3_w=0;
	#(102+($urandom%100)*10)
	start3_w=1;
	#10
	start3_w=0;
end
//slave侧信号
AXI4_Lite s0(.aclk(clk),.aresetn(rst_n));
AXI4_Lite s1(.aclk(clk),.aresetn(rst_n));
//AXI4_Lite s(.aclk(clk),.aresetn(rst));
//4个主机的接口信号定义
AXI4_Lite m0(.aclk(clk),.aresetn(rst_n));
AXI4_Lite m1(.aclk(clk),.aresetn(rst_n));
AXI4_Lite m2(.aclk(clk),.aresetn(rst_n));
AXI4_Lite m3(.aclk(clk),.aresetn(rst_n));
AXI4_Lite axilite(.aclk(clk),.aresetn(rst_n));
//
logic m_sel_w;        
logic m0_sel_w;
logic m1_sel_w;
logic m2_sel_w;
logic m3_sel_w;
logic m_sel_r;
logic m0_sel_r;
logic m1_sel_r;
logic m2_sel_r;
logic m3_sel_r;
logic done0;
logic done1;
logic done2;
logic done3;
logic start0_w;
logic start1_w;
logic start2_w;
logic start3_w;
logic start0_r;
logic start1_r;
logic start2_r;
logic start3_r;
logic [2:0] cur_master_w;                       //当前哪个主机占有总线
logic [2:0] cur_master_r;
//
SlaveMux SMux(
.s0(s0),               //slave0
.s1(s1),               //slave1
.s(axilite), 
.m_sel_w(m_sel_w),                    //根据该信号决定哪个从机
.m_sel_r(m_sel_r)
);
//slave-->master mux
MasterMux MMux(
.m0(m0),
.m1(m1),
.m2(m2),
.m3(m3),
.m(axilite),
.m0_sel_w(m0_sel_w),
.m1_sel_w(m1_sel_w),
.m2_sel_w(m2_sel_w),
.m3_sel_w(m3_sel_w),
.m_sel_w(m_sel_w),
.m0_sel_r(m0_sel_r),
.m1_sel_r(m1_sel_r),
.m2_sel_r(m2_sel_r),
.m3_sel_r(m3_sel_r),
.m_sel_r(m_sel_r),
.cur_master_w(cur_master_w),                 //仲裁结果，据此决定哪个主机的信号给m_*,或者将m_*反馈回给哪个主机
.cur_master_r(cur_master_r)
);
//写仲裁器
axiw_arbitor ArbitorW(
    .clk(clk),
    .rst_n(rst_n),
    //来自主机
    .m0_awvalid(m0.awvalid),
    .m1_awvalid(m1.awvalid),
    .m2_awvalid(m2.awvalid),
    .m3_awvalid(m3.awvalid),
    //来自从机
    .m0_bvalid(m0.bvalid),
    .m1_bvalid(m1.bvalid),
    .m2_bvalid(m2.bvalid),
    .m3_bvalid(m3.bvalid),
    //来自主机
    .m0_bready(m0.bready),
    .m1_bready(m1.bready),
    .m2_bready(m2.bready),
    .m3_bready(m3.bready),
    //仲裁结果
    .cur_master(cur_master_w)           //0表示当前总线被主机0占用,以此类推
);
//读仲裁器
AXI_R_Arbitor ArbitorR(
.clk(clk),
.rst_n(rst_n),
//req
.m0_arvalid(m0.arvalid),
.m1_arvalid(m1.arvalid),
.m2_arvalid(m2.arvalid),
.m3_arvalid(m3.arvalid),
.m0_rvalid(m0.rvalid),
.m1_rvalid(m1.rvalid),
.m2_rvalid(m2.rvalid),
.m3_rvalid(m3.rvalid),
.m0_rready(m0.rready),
.m1_rready(m1.rready),
.m2_rready(m2.rready),
.m3_rready(m3.rready),
//
.cur_master(cur_master_r)
    );
//********************************************************两个从机************************************************************
//slave0
slave 
#(.N(0))
S0(.s_axilite(s0));
//slave1
slave 
#(.N(1))
S1
(.s_axilite(s1));
//******************************************************************4个主机****************************************************
master 
#(.N(0),
  .TEST_LEN(64))
M0
(
.start_w(start0_w),
.start_r(start0_r),
.sel_w(m0_sel_w),
.sel_r(m0_sel_r),
.m(m0),
.done(done0)
);
master 
#(.N(1),
  .TEST_LEN(64))
M1
(
.start_w(start1_w),
.start_r(start1_r),
.sel_w(m1_sel_w),
.sel_r(m1_sel_r),
.m(m1),
.done(done1)
);
master 
#(.N(2),
  .TEST_LEN(64))
M2
(
.start_w(start2_w),
.start_r(start2_r),
.sel_w(m2_sel_w),
.sel_r(m2_sel_r),
.m(m2),
.done(done2)
);
master 
#(.N(3),
  .TEST_LEN(64))
M3
(
.start_w(start3_w),
.start_r(start3_r),
.sel_w(m3_sel_w),
.sel_r(m3_sel_r),
.m(m3),
.done(done3)
);
	
endmodule
